Active matrix liquid crystal light valve with drive circuit

ABSTRACT

A technology is disclosed in which the voltage of a drive signal pulse to be supplied to a switch, which transfers a signal to be supplied to a liquid crystal cell, is raised. A plurality of lines for the signals to be supplied to a switch array which transfers the signal to be supplied to the liquid crystal cell is provided so as to supply drive signal pulses for operating switches which correspond to a plurality of the lines while time sequentially overlapping the drive signal pulses.

This application is a continuation of application Ser. No. 08/176,515filed Jan. 3, 1994, now abandoned, which is a continuation ofapplication Ser. No. 08/010,629 filed Jan. 28, 1993, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an active matrix liquid crystal lightvalve (AMLCV) for switching a liquid crystal cell by an active elementthereof, to a liquid crystal display apparatus (LCD) having the lightvalve, and to an image information processing apparatus having the LCD.

2. Related Background Art

Hitherto, a liquid crystal display (LCD) having an active element hasbeen, as an AMLCV, widely used in a structure which comprises twistednematic (TN) liquid crystal, and have been marketed as a flat paneldisplay or a projection TV monitor. The active element typified by athin film transistor (TFT), or a diode or a MIM (Metal Insulator MetalElement) enhances the optical switch response of TN liquid crystal whichsuffers from relatively slow response, by keeping a state, in which theTN liquid crystal is being applied with voltage, for a period longerthan the actual line selection period. Furthermore, the active elementcauses liquid crystal device such as the TN liquid crystal having nomemory characteristics (self-holding characteristics) to have asubstantial memory state for each unit cell for one frame by keeping theaforesaid voltage applied state. The LCD has excellent displaycharacteristics because it is theoretically freed from crosstalk betweenlines and between pixels thereof.

Recently, ferroelectric liquid crystal (FLC) revealing the responsespeed higher than that of the TN liquid crystal by a degree of severaldigits has been developed energetically, resulting in display panels andlight valves using the same to be disclosed. In the aforesaidcircumstance, there is a possibility that a further excellent displaydevice can be obtained by driving the FLC by the active matrix device.As an example structured by combining the FLC and the TFT has beendisclosed in, for example, U.S. Pat. No. 4,840,426 and in Proceeding ofthe SID, vol. 30, 1989 "Ferroelectric Liquid-Crystal Video Display" vol.30, 1989.

FIG. 11 illustrates a conventional liquid crystal display circuit.

The circuit shown in FIG. 11 comprises a unit pixel composed of a commonelectrode COM, a liquid crystal cell 701 filled with liquid crystalmaterial between its pixel electrodes CE, and a pixel TFT 702. Thecircuit still further comprises a signal line 703, a line buffer 704, ashift pulse switch 708, and a horizontal shift register 705 fortransmitting video signals. The circuit further comprises a gate line711 and a vertical shift register 706 for transmitting gate signals. Thevideo signals are received by a signal input terminal 707 so as to besequentially transferred to each pixel or each line while having theirtiming shifted.

FIG. 12 illustrates the timing of drive pulses for use in theconventional active matrix liquid crystal display device shown in FIG.11. FIG. 12 illustrates the timing of the drive pulses for use in a linesequential drive method. That is, video signal Sv to be recorded on theliquid crystal is recorded in such a manner that video signals for oneline are recorded on the buffer portion via a shift pulse switch 708which is operated by the horizontal shift register 705 arranged totransmit an output in synchronization with the frequency of the videosignal Sv. After the video signals for all of the pixels for one linehave been recorded to the line buffer portion 704, the video signal isrecorded to each liquid crystal cell via a pixel switch, which has beenswitched on by an output switch of the line buffer portion 704 and thevertical shift register 706. The signals are usually transferred to eachliquid crystal cell during a blanking period of a horizontal scanningperiod or transferred collectively to a certain horizontal line inresponse to pulse φt. At the aforesaid timing, the video signals aresequentially transferred to each line.

When molecules of the liquid crystal, which forms the cell, move inaccordance with the voltages of the signals thus transferred, thetransmittance of the liquid crystal cell is changed in accordance withthe direction of the deflection plate individually provided to have arelationship of a cross polarizer. The aforesaid state is shown in FIG.13.

The voltage of the signal shown in the axis of abscissa of FIG. 13 ismeant different facts depending upon the type of liquid crystal. Forexample, the values are defined to be effective voltage values (Vrms) inthe case of the TN liquid crystal. The qualitative description of theaforesaid value will be made with reference to FIG. 14. In order toprevent a fact that DC components are applied to the liquid crystal fora long time, there is a method in which the polarity of the signalvoltage is altered for each frame at the time of supplying the signal.In this case, the liquid crystal acts in accordance with the AC voltagecomponent shown by a portion designated by a diagonal line. Therefore,execution voltage V_(rms) is expressed as follows when the time for twoframes is t_(F) and the signal voltage to be transferred to the liquidcrystal is V_(LC) (t): ##EQU1##

On the other hand, the FLC is ordinarily driven by DC voltage. In a casewhere FLC of a type having a bistable state is employed (it ispreferable that chiral smectic liquid crystal be used, furtherpreferable chiral smectic liquid crystal such as phase C (SmC*), phase H(SmH*), SmI*, SmF* or SmG* chiral smectic liquid crystal be used), drivewaveforms shown in FIG. 15 are offered. That is, the signal voltage isreset to either of the bistable states in accordance with reset voltageV_(R) before the signal is written, and then writing voltage signal(V_(M)) is applied. Also the signal voltage contributing to thetransmittance shown in FIG. 13 is designated by diagonal lines. In amanner different from the TN liquid crystal, the DC component of thewriting voltage is the signal voltage as it is.

Although the voltage of the pixel electrode is changed in accordancewith the signal voltage if the drive method shown in FIG. 12 is used, itis always positive with respect to the potential of the common electrodeof the liquid crystal similarly to the case where a DC voltage componentis always applied to the liquid crystal cell. In the case where the TNliquid crystal is used as the liquid crystal material, the aforesaid DCcomponent causes a problem to arise in that the liquid crystal moleculescan be burnt.

Methods of removing the DC voltage component is typified by a method ofreversing the signal voltage for each frame arranged as shown in FIG.14. The signal voltage at the N-th time is so applied as to be positivewith respect to the potential of the common electrode, while the signalvoltage at the (N+1)-th time is so applied as to be negative. Byreversing the polarity of the signal voltage with respect to thepotential of the common electrode for each frame as described above, theDC voltage components to be applied to the liquid crystal cell are setoff so that burning of the liquid crystal molecules can be prevented.

Similarly, a method of reversing the same for each 1H and a method ofreversing the same for each pixel may be employed. However, theaforesaid reversing drive method arises the following problems.

Assuming that the maximum value of the signal voltage is V_(MAX), theshift register portion must have, regardless of the type of thereversing method, performance capable of transferring a signal having anamplitude which is two times the VMAX if the reversing drive method isemployed. Therefore, the shift register portion must, of course, be ableto withstand the ON/OFF voltage.

As a means for relaxing the required condition about the voltageresistance, it might be feasible to employ a method in which the maximumamplitude of the signal voltage is reduced. However, the aforesaid meanscannot be preferably adapted to a high vision display which is expectedto be rapidly widely used in the future and which must have excellentprecision because it is difficult to keep the gradation as can beunderstood from FIG. 13.

Another method can be employed in which a voltage-resisting MOStransistor such as a LDD (Lightly Doped Drain) serving as a switch isused as a transistor which constitutes the shift register. However, theaforesaid voltage-resisting MOS transistor, which is being developedcurrently, arises a problem in that the mutual conductance (gm) islowered due to enlargement of the resistance, which is in series appliedto the source and the drain although it is able to improve the voltageresistance. As described above, the LCV must be, as an active device,driven at further high speed as in the case of the high vision display.Therefore, the TFT must have a larger gm. What is worse, the MOStransistor having the voltage resistance as described above can bemanufactured only from a complicated process, causing problems to arisein that the yield deteriorates when it is used to constitute the shiftresistor and that the manufacturing cost cannot be reduced.

There is another desire of improving the drive speed in addition to theaforesaid desire of improving the voltage resistance in order to displayan excellent image. In particular, it is necessary to raise the speed ofwriting data to the line buffer in the case where the line sequentialdrive method is employed. Although it might be considered to raise thefrequency of the shift pulse in order to achieve this, the circuit shownin FIG. 11 and the drive method shown in FIG. 12 cannot satisfactorilyraise the aforesaid frequency.

In a circumstance in which the quantity of information is enlarged, theaforesaid problem causes software to bear a larger load or causeshardware such as the memory quantity and the microprocessor (MPU) tobear a larger load.

SUMMARY OF THE INVENTION

An object of the present invention is to overcome technological problemsrelated to the aforesaid voltage resistance by improving the drivecircuit.

A further object of the present invention is to overcome technologicalproblems taken place in processing signals and independently from theaforesaid problem of the voltage resistance by improving the drivecircuit and drive timing.

A still further object of the present invention is to reduce the size ofperipheral equipment or to simplify software.

The aforesaid first to third objects can be achieved by an active matrixliquid crystal light valve having a plurality of cells each includingliquid crystal and an active element, the active matrix liquid crystallight valve comprising: a circuit which operates a switch fortransferring signals to be respectively supplied to the cells and whichhas a shift register and voltage raising means for raising the voltageof the shift register.

The aforesaid first to third objects can be achieved by a liquid crystaldisplay and an image information processing apparatus having theaforesaid display, the liquid crystal display comprising liquid crystaldisplay means, in which a plurality of cells each having liquid crystaland an active element are disposed in a matrix manner, and a drivecircuit for operating the display means, wherein the drive circuitincludes a switch for transferring signals to be supplied to a pluralityof the cells, a shift register for generating a shift pulse, a voltageraising circuit for raising the voltage of the shift pulse of the shiftregister, and the output from the voltage raising circuit is supplied tothe switch, so that the switch is operated.

The aforesaid first to third objects can be achieved by a liquid crystaldisplay and an image information processing apparatus having theaforesaid display, the liquid crystal display comprising liquid crystaldisplay means, in which a plurality of cells each having liquid crystaland an active element are disposed in a matrix manner, and a drivecircuit for operating the display means, wherein the drive circuitincludes a switch array for transferring image signals to be supplied toa plurality of the cells, and a pulse generating circuit for generatingtime sequential pulses for sequentially operating the switch array, anda plurality of signal lines are provided which supply the signals to theswitch array so that the time sequential pulses are supplied to theswitch array while at least partially overlapping said time sequentialpulses.

Other and further objects, features and advantages of the invention willbe appear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a drive circuit for use in an active matrix liquidcrystal light valve according to Embodiment 1 of the present invention;

FIG. 2 is an operation timing chart of the drive circuit according toEmbodiment 1 of the present invention;

FIG. 3 is a timing chart for the drive circuit according to Embodiment 1and partially using a PMOS transistor;

FIG. 4 illustrates a drive circuit for use in an active matrix liquidcrystal light valve according to Embodiment 2 of the present invention;

FIG. 5 is an operation timing chart of the drive circuit according toEmbodiment 2 of the present invention;

FIG. 6 illustrates a drive circuit for use in an active matrix liquidcrystal light valve according to Embodiment 3 of the present invention;

FIG. 7 is an operation timing chart of the drive circuit according toEmbodiment 3 of the present invention;

FIG. 8 illustrates a drive circuit for use in an active matrix liquidcrystal light valve according to Embodiment 4 of the present invention;

FIG. 9 is an operation timing chart of the drive circuit according toEmbodiment 4 of the present invention;

FIG. 10 is a schematic view which illustrates the structure of an imageinformation processing apparatus which uses the liquid crystal lightvalve according to the present invention;

FIG. 11 illustrates a circuit for a conventional liquid crystal display;

FIG. 12 illustrates the timing of drive pulses for the active matrixliquid crystal display;

FIG. 13 is a graph which illustrates the correlation between thetransmittance of a TN liquid crystal cell and the signal voltage;

FIG. 14 illustrates the drive waveform in the active matrix liquidcrystal display which uses the TN liquid crystal;

FIG. 15 illustrates the drive waveform in the active matrix liquidcrystal display which uses ferroelectric liquid crystal;

FIG. 16 illustrates a drive circuit for use in an active matrix liquidcrystal light valve according Embodiment 5 of the present invention; and

FIG. 17 is an operation timing chart of the drive circuit according toEmbodiment 5 of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first aspect of the present invention is arranged in such a mannerthat the voltage of drive signal pulses supplied to a switch fortransferring the signal to be applied to a liquid crystal cell israised. As a result of the aforesaid structure, the complicatedstructure required to improve the voltage resistance of a transistor orthe like which constitutes the shift register can be omitted. It leadsto a fact that devices revealing excellent performance can bemanufactured while maintaining an excellent yield.

A second aspect of the present invention is arranged in such a mannerthat a plurality of lines are connected to a switch for transferringsignals to be supplied to a liquid crystal cell, and drive signal pulsesare supplied to the switch while being overlapped in a time sequentialmanner in order to drive the switch adapted to a plurality of the lines.As a result of the structure thus arranged, the speed of processing theimage (video) signals can be raised, also causing an effect to beobtained in that devices revealing excellent performance can bemanufactured while maintaining an excellent yield. Furthermore, the sizeof software and hardware of peripheral equipment can be reduced.

The present invention can be used in liquid crystal printers, lightvalves for liquid crystal displays, and image processing apparatuses onwhich the aforesaid light valves are mounted. The active element, thetransferring switch, the shift register and the voltage-raising meansare preferably integrally formed on one substrate. It is preferable thatthe substrate has a semiconductor region on an insulating film thereof.The reason for this lies in that use of the substrate of the aforesaidtype enables a light transmissive type liquid crystal light valveincluding a peripheral circuit to be formed easily.

It is preferable that the voltage raising means according to the firstaspect of the present invention be formed by using a transistor, or acapacitor or a diode.

A plurality of the lines according to the second aspect of the presentinvention are arranged to receive a plurality of element signals whichconstitute the video signal, the element signal being synthesized so asto be one video signal. In particular, use of color decompositionsignals such as a red signal, a green signal and a blue signal as theelement signals enables the signal processing speed for forming acomplicated color image to be easily raised.

More preferably, writing data to the line buffer can be completedquickly if the second aspect is adopted so as to be adapted to the linesequential drive, causing a sufficient time for performing the timesequential process of other signals in parallel to be possessed.

Then, preferred embodiments of the present invention will now bedescribed in detail. It is understood that the present disclosure of thepreferred form has been changed in the details of construction and thecombination and arrangement of parts may be resorted to withoutdeparting from the spirit and the scope of the invention as hereinafterclaimed.

Embodiment 1

FIG. 1 illustrates a drive circuit for use in an active matrix deviceaccording to this embodiment. Referring to FIG. 1, reference numeral 101represents a shift register, and P1 to P7 represent output terminals ofthe shift register 101. Reference numeral 102 represents a first MOStransistor having the gate and the source which are connected to thefirst output terminal P1 of the shift register 101. Reference numeral103 represents a first capacitor having a first electrode connected tothe second output terminal P2 of the shift register 101. Referencenumeral 104 represents a second MOS transistor having the gate connectedto the third output terminal P3 of the shift register 101 and having thesource connected to a reset power supply line 105 connected to areference power source V_(RS) for supplying resetting reference voltage.The drain of the first MOS transistor, the second electrode of the firstcapacitor 103 and the drain of the second MOS transistor are connectedto one another so as to be a first output terminal 01. A structureconstituted similarly to that described above, the MOS transistor andthe capacitor are connected to the third output terminal P3, the fourthoutput terminal P4 and the fifth output terminal P5 of the shiftregister so as to be a second output terminal 02. Then, connections areperformed similarly to the description above while performing shiftingby a degree of two terminals. Reference numeral 106 represents aswitching transistor which is controlled in response to a signal fromthe shift register 101.

The specific operation will now be described with reference to anoperation timing chart shown in FIG. 2.

The outputs from the shift register 101 are, as can be understood fromP1 to P7 shown in FIG. 2, sequentially transmitted from thecorresponding terminals while being freed from overlap in terms of time.The potential of the output terminal 01 is first raised to a level whichis lower than the output voltage from P1 by a degree corresponding tothe threshold value of the MOS transistor 102. In response to the signalfrom P2, the potential is then raised by a degree corresponding to thevoltage which is the result of multiplication of the signal voltage P2and the capacitance division ratio between the capacitor 103 and thegate capacity of the transistor 106 via the capacitor 103. Assuming thatthe output amplitude of P1 to P7 is 7V, the threshold voltage of thefirst MOS transistor 102 is 7V and the capacitance division ratio of thegate capacity of the capacitor 103 and that of the transistor 106 is0.9, the voltage to be applied to the gate of the switching transistor106 is, as expressed by the following equation, raised to 12.3 V, whichis 1.76 times the operation voltage 7 V of the shift register 101.

    Output terminal voltage=(7-1)+7×0.9=12.3 V

The circuit thus arranged is able to generate a high voltage level of12.3 V while keeping the power supply voltage in the shift register 101and to be applied to each transistor in this circuit at the aforesaidlow level of 7 V. Therefore, a signal, the amplitude of which is 11V,can be treated.

A timing chart realized in the case where a PMOS is used as theswitching transistor 106 is shown in FIG. 3. If the PMOS is used, asimilar effect can be obtained.

Embodiment 2

FIG. 6 illustrates a circuit for use in a third embodiment. Thisembodiment is arranged in such a manner that the circuit according tothe present invention is connected to the first output terminal P1, thesecond output terminal P2 and the third output terminal P3 of the shiftregister, and then the same is sequentially connected to the secondoutput terminal P2, the third output terminal P3 and the fourth terminalP4 while being shifted by a degree of one terminal. The operation timingof this circuit is shown in FIG. 5. As can be understood from FIG. 5,outputs from the circuit according to this embodiment are overlapped fora certain period, so that operation speed can be raised in comparison toEmbodiment 1 by overlapping the timing of the outputs in the case wherea plurality of signal lines are connected by the switching transistor106, for example in a case where signal lines corresponding R, G and Bare used in a color panel.

Embodiment 3

FIG. 6 illustrates a circuit for use in a third embodiment. According tothe Embodiment 1, the period in which a desired high potential can bemaintained is limited to the period in which the signal P2 is outputted.However, this embodiment enables the potential of the first electrode ofthe capacitor to be maintained as shown in FIG. 7 although the output ofthe signal P2 has been ended and also the potential of the output fromthe second electrode can be maintained at a desired high level until thenext signal P3 is supplied by arranging the structure in such a mannerthat a third MOS transistor 610 is inserted into a portion between thefirst electrode of the first capacitor and the output terminal P2 of theshift register, the source and the gate of the aforesaid MOS transistorare connected to the output terminal P2 and the drain of the same isconnected to the first electrode of the first capacitor. As a result,the period in which the switching transistor is able to transfer thesignal can be lengthened.

A reset transistor 602 is connected to the first electrode of the firstcapacitor, so that the potential of the first electrode is reset whenthe signal P3 is supplied.

Embodiment 4

FIG. 8 illustrates a circuit for use in a fourth embodiment of thepresent invention. This embodiment is constituted in such a manner thatthe voltage raising circuit is formed by using a charge pumping circuit.The circuit according to the fourth embodiment of the present inventioncomprises a fourth MOS transistor 801, a fifth MOS transistor 802, asixth MOS transistor 803 and a second capacitor 804. The source of thefourth MOS transistor 801 is connected to a power source line VDD 805,while the gate is connected to the output terminal P1 of the shiftregister. Furthermore, the drain of the fourth MOS transistor 801, thesource and the gate of the fifth MOS transistor 802 are connected to thefirst electrode of the second capacitor 804. The second electrode of thesecond capacitor 804 is connected to the output terminal P2, the sourceof the sixth MOS transistor 803 is connected to a power supply line VSS806, the gate of the same is connected to the output terminal P3 of thesift register, and the drain of the fifth MOS transistor 802 and that ofthe sixth MOS transistor 803 are connected to each other so as to be anoutput terminal. The operation timing according to the fourth embodimentof the present invention is shown in FIG. 9. First, the signal P1 actsto raise the potential of the drain terminal of the fourth MOStransistor 801. Then, the signal P2 acts to further raise the potentialvia the capacitor 804 so as to output it. Then, resetting is performedin response to the signal P3. Also according to this embodiment, aneffect similar to that obtainable from the aforesaid embodiments can beobtained.

The output (the video signal) from the switching transistor 106according to the aforesaid Embodiments 1 to 4 is supplied to the signalline 704 via the line buffer 704 shown in FIG. 11 in the case where theline sequential drive method is employed. In another case where drivingis sequentially performed in a time sequential manner for each pixel,the output is directly supplied to the signal line 704 in such a mannerthat the output does not pass through the line buffer 704.

The circuit according to Embodiments 1 to 4 is formed on a semiconductorsubstrate.

FIG. 10 is a schematic view which illustrates an image informationprocessing apparatus which employs the AMLCD according to the presentinvention.

Reference numeral 1 represents an AMLCD having a display portion 5formed at the central portion of a substrate 6 thereof. FIG. 10 is apartially enlarged view of the pixel portions given reference numerals 4and 4'. A drive circuit including the shift register is disposed aroundthe display portion 5. Horizontal drive circuits 3 and 3" connected tothe signal line and arranged to supply the video signals are connectedto the gate line, the horizontal drive circuits 3 and 3' respectivelybeing disposed above and below the display portion. Drive circuits 2 and2' for generating line selection signals are disposed to the right andleft of the display portion 5.

The AMLCD 1 is structured in such a manner that the aforesaid drivecircuits are connected to drive control circuit 10 mounted on anindividual substrate. The drive control circuit 10 includes a circuitfor dividing one video signal into a plurality of element signals (forexample, S_(VR), S_(VG) and S_(VB)) in the case where it is designed tobe adapted to Embodiments 2 to 4.

The drive control circuit 10 is, together with a lighting controlcircuit including a power source 12 and an inverter for controllinglighting of the light source, connected to a central processing circuit14.

The image information processing apparatus according to this embodimentfurther comprises an optical system 22 including a lens through whichimage information is received, an image sensor 21 including aphotoelectric conversion element and its drive circuit 20.

In addition, image information obtained by the image sensor 21 and/ordisplayed image information are recorded to a recording medium by arecording control circuit 30 including a recording head 31.

The active matrix liquid crystal display 1 can be formed on onesubstrate while including the liquid crystal device, the liquid crystaldrive circuit and its peripheral drive circuit by using a semiconductorsubstrate having a single crystal Si layer and manufactured by thefollowing method. The method will now be described.

The single crystal Si layer of the semiconductor substrate is formed byusing a porous Si substrate obtained by making a single crystal Sisubstrate to be porous.

As a result of an observation performed by using a transmissive typeelectronic microscope, the porous Si substrate have pores, the meandiameter of which is about 600 Å formed therein. Furthermore, althoughthe density is less than the half of that of the single crystal Si,single crystallinity is maintained. Therefore, a single crystal Si layercan be allowed to epitaxial-grow on a porous layer. However, the formedpores are again arranged if the temperature is higher than 1000° C.,causing the characteristics of the acceleration etching to be lost.Therefore, it is considered preferable to cause the Si layer toepitaxial-grow by a molecular beam epitaxial grow method, a plasmaenhanced CVD method, a thermal CVD method, a photo CVD method, a biassputtering method or a liquid-phase crystal growth method.

A method of allowing the single crystal layer to epitaxial-grow after aP-type Si has been made to be porous type will now be described.

First, a Si single crystal substrate is prepared, and it is made to be aporous type by an anode forming method in which a HF solution is used.Although the density of the single crystal Si is 2.33 g/cm³, the densityof the porous Si substrate can be changed to 0.6 to 1.1 g/cm³ bychanging the concentration of the HF solution to 20 wt % to 50 wt %. Theporous layer can easily be formed in the P-type Si substrate because ofthe following reasons:

The porous Si was found during research of electrolytic polishing. In adissolution reaction of Si in the anode formation, the anode reaction ofSi in a HF solution requires positive holes, the anode reaction beingexpressed as follows:

    Si+2HF+(2-n) e.sup.+ →SiF.sub.2 +2H.sup.+ +ne.sup.-

    SiF.sub.2 +2HF→SiF.sub.4 +H.sub.2

    SiF.sub.4 +2HF→H.sub.2 SiF.sub.6

or

    Si+4HF+(4-λ)e.sup.+ →SiF.sub.4 +4H.sup.+ +λe.sup.-

    SiF.sub.4 +2HF→H.sub.2 SiF.sub.6

where e⁺ and e⁻ respectively denote a positive hole and electron, and nand λ respectively denote the number of positive holes required todissolve one Si atom. If n>2 or λ>4, the porous Si can be formed.

Therefore, it can be said that the P-type Si having the positive holescan easily be made to be the porous type.

Another fact that a high density N-type Si can be made to be a poroustype has been reported. Hence, the porous Si can be made to be theporous type regardless of the type of the Si.

Since the porous layer has a large quantity of gaps formed therein, itsdensity is reduced to the half or less. As a result, the surface areasignificantly increases as compared with the volume, causing the speed,at which it is chemically etched, to be raised considerably incomparison to the speed at which an ordinary single crystal layer isetched.

Then, the conditions for making the single crystal Si to be porous typeby anode forming will now be described. It should be noted that thestarting material to form the porous Si by anode forming is not limitedto the single crystal Si, but Si of a type having another crystalstructure may be employed.

Applied voltage: 2.6 V

Current density: 30 mA·cm⁻²

Anode forming solution: HF:H₂ O:C₂ H₅ OH=1:1:1

Time: 2.4 hours

Thickness of porous Si: 300 μm

Porosity: 56%

Then, Si is allowed to epitaxial-grow on the porous Si substrate thusformed, so that a single crystal Si thin film is formed. It ispreferable that the thickness of the single crystal Si thin film be 50μm or less, more preferably 20 μm or less.

Then, the surface of the single crystal Si thin film is oxidized, and asubstrate which finally forms the substrate is prepared, and theoxidized film on the surface of the single crystal Si and the aforesaidsubstrate are bonded to each other. As an alternative to this, thesurface of a single crystal Si substrate is oxidized, and it is bondedto the single crystal Si layer. The reason why the aforesaid oxidizedfilm is formed between the substrate and the single crystal Si layerlies in that the interfacial level generated from the base interface ofa Si active layer can be lowered in the oxidized layer interface ascompared with the aforesaid glass interface in the case where glass isused as the substrate and therefore the characteristics of theelectronic device can be significantly improved. As an alternative tothis, only a single crystal Si thin film, from which the porous Sisubstrate has been removed by selective etching, may be bonded to a newsubstrate. Although the aforesaid members can be bonded closely due tovan der Waals force simply by making them come in contact with eachother at the room temperature after their surfaces have been cleaned,they are heated at a temperature of 200 to 900° C. under nitrogenatmosphere, preferably 600 to 900° C.

Then, a Si₃ N₄ layer is deposited on the overall surface of the twosubstrates bonded so as to serve as an etching prevention film, and onlythe Si₃ N₄ layer formed on the surface of the porous Si substrate isremoved. An apiezon wax may be used in place of the aforesaid Si₃ N₄layer. Then, the porous Si substrate is completely removed by etching orthe like, so that the semiconductor substrate having the thin filmsingle crystal Si layer can be obtained.

Then, a selective etching method for electroless- and wet-etching onlythe porous Si substrate will now be described.

As etching liquid which does not etch crystal Si but which is able toselectively etch only the porous Si, any of the following materials canbe preferably employed: buffered hydrofluoric acids such as ahydrofluoric acid, an ammonium fluoride (NH₄ F) and a hydrogen fluoride(HF); a mixture solution of a hydrofluoric acid or a bufferedhydrofluoric acid prepared by adding a hydrogen peroxide solution; amixture solution of a hydrofluoric acid or a buffered hydrofluoric acidprepared by adding alcohol; or a mixture solution of a hydrofluoric acidor a buffered hydrofluoric acid prepared by adding a hydrogen peroxideand alcohol. The bonded substrates are wetted with the aforesaidsolution so that etching is performed. The etching speed depends uponthe concentration of the hydrofluoric acid, the buffered hydrofluoricacid and the hydrogen peroxide solution and upon the temperature. Byadding the hydrogen peroxide solution, the oxidation of Si isaccelerated and therefore the reaction speed can be raised as comparedwith the method in which they are not added. Furthermore, the reactionspeed can be controlled by changing the ratio of the hydrogen peroxide.By adding alcohol, bubbles of a gas generated due to the reaction takenplace in the etching process can be immediately removed from the etchedsurface while eliminating a necessity of performing stirring. Therefore,the porous Si can be uniformly and efficiently etched.

It is preferable that the concentration of HF contained in the bufferedhydrofluoric acid be ranged from 1 to 95 wt %, preferably from 1 to 85wt %, and more preferably from 1 to 70 wt %. It is preferable that theconcentration of NH₄ F contained in the buffered hydrofluoric acid beranged from 1 to 95 wt %, preferably from 5 to 90 wt %, and morepreferably from 5 to 80 wt %.

It is preferable that the concentration of HF with respect to theetching solution be ranged from 1 to 95 wt %, preferably 5 to 90 wt %and more preferably from 5 to 80 wt %.

The concentration of H₂ O₂ with respect to the etching solution beranged from 1 to 95 wt %, preferably 5 to 90 wt %, and more preferably10 to 80 wt % while offering the effect of the hydrogen peroxidesolution.

The concentration of alcohol with respect to the etching solution be 80wt % or less, preferably 60 wt % or less, and more preferably 40 wt % orless while offering the effect of the alcohol.

It is preferable that the temperature be 0 to 100° C., preferably 5 to80° C., and more preferably 5 to 60° C.

The alcohol for use in the process according to this embodiment is notlimited to ethyl alcohol, but it may be alcohol such as isopropylalcohol which does not arise a practical problem during themanufacturing process and which enables the effect required for theadded alcohol to be obtained.

The semiconductor substrate thus obtained has the single crystal Silayer formed similarly to that of an ordinary wafer in such a mannerthat it is flattened and thinned to have a large area on the overallsurface of the substrate.

The single crystal Si layer of the semiconductor substrate is separatedby a partial oxidation method or by etching so as to be formed into anisland, so that impurities are doped and a p- or n-channel transistor isformed.

Embodiment 5

FIGS. 16 and 17 respectively are a view which illustrates a drivecircuit for use in a liquid crystal light valve according to the presentinvention and a timing chart of the drive circuit.

This embodiment is arranged to partially improve Embodiment 4 and theresidual structures are the same as those according to Embodiment 4.

The circuit is arranged in such a manner that the terminals of the shiftregister are connected while being shifted rearwards in such a way thatthe gate of the MOS transistor 803 is connected to the terminal P4, sothat the resetting timing (ON) of a terminal of the voltage raisingcircuit and the setting timing (OFF) of the next terminal are madeopposite in terms of time so that overlapping period T₀₁ and T₀₂ aresequentially created. Furthermore, a register which acts at a highfrequency is employed as the shift register 101. As a result, the speedof processing signals to be written to the output side of the switch 106can be raised.

Although the voltage raising circuit and the overlap drive are combinedaccording to this embodiment similarly to Embodiments 2 and 3, anotherstructure may be employed in which no voltage raising circuit is usedand the shift pulses of the shift register are simply overlapped whenthey are supplied while eliminating the process of raising the voltage.

Although the invention has been described in its preferred form with acertain degree of particularly, it is understood that the presentdisclosure of the preferred form has been changed in the details ofconstruction and the combination and arrangement of parts may beresorted to without departing from the spirit and the scope of theinvention as hereinafter claimed.

What is claimed is:
 1. An active matrix liquid crystal light valvehaving a plurality of cells each including liquid crystal and an activeelement, said active matrix liquid crystal light valve comprising:acircuit which operates a transistor switch for transferring signalsthrough a source and a drain of said transistor switch to berespectively supplied to said cells and which has a shift register andvoltage raising means connected to a gate of said transistor switch forraising a voltage of said shift register, wherein: said voltage raisingmeans has a first MOS transistor, a second MOS transistor, and acapacitor; and a gate and a source of said first MOS transistor areconnected to a first output of said shift register, a first electrode ofthe capacitor is connected to a second output of said shift register, agate of said second MOS transistor is connected to a third output ofsaid shift register, a source of said second MOS transistor is connectedto a resetting power supply line individually provided, and a drain ofsaid first MOS transistor, a second electrode of the capacitor and adrain of said second MOS transistor are connected to one another.
 2. Anactive matrix liquid crystal light valve having a plurality of cellseach including liquid crystal and an active element, said active matrixliquid crystal light valve comprising:a circuit which operates atransistor switch for transferring signals through a source and a drainof said transistor switch to be respectively supplied to said cells andwhich has a shift register and voltage raising means connected to a gateof said transistor switch for raising a voltage of said shift register,wherein: said voltage raising means has a fourth MOS transistor, a fifthMOS transistor, a sixth MOS transistor, and a second capacitor; a sourceof said fourth MOS transistor is connected to a power supply line, agate of said fourth MOS transistor is connected to a first outputterminal of said shift register, a drain of said fourth MOS transistor,a source and a gate of said fifth MOS transistor, and a first electrodeof said second capacitor are connected to each other; and a secondelectrode of said second capacitor is connected to a second outputterminal of said shift register, a source of said sixth MOS transistoris connected to a resetting power supply line, a gate of said sixth MOStransistor is connected to a third output terminal of said shiftregister, and a drain of said fifth MOS transistor and a drain of saidsixth MOS transistor are connected to each other.